Aufgrund eines Problems in der Intel® Quartus® Prime Pro Edition Softwareversion 22.3 kann das Skript "ptp_fw.tcl", das in den Designbeispielen für mehrspurige PTP-Varianten des F-tile Ethernet Intel® FPGA Hard IP bereitgestellt wird, falsche rx_tam_adjust Werte liefern.
Führen Sie die folgenden Schritte aus, um dieses Problem zu umgehen:
- Öffnen Sie das PTP-Firmware-Skript, das Sie im Ordner <generated example design>/hardware_test_design/hwtest/altera/ptp/ptp_fw.tcl finden.
- Suchen und ersetzen Sie die folgenden Codezeilen:
VON | AN |
# b) Pulseinstellung berechnen for {set fl 0} {$fl < $::FL} {incr fl} { |
# b) Berechnen Sie die Impulsanpassung und prüfen Sie, ob FECs cw_pos Rollover zwischen FEC-Lane, die von derselben Transceiver-Lane empfangen wird, erfolgt for {set fl 0} {$fl < $::FL} {incr fl} { Set cond2a [expr ($rx_FEC_CW_POS_FL($fl__minus) > $rx_FEC_CW_POS_FL($fl))] if {$cond 1a && $cond 1b} { |
return [array get rx_xcvr_if_pulse_adj] |
Setzen Sie l_rx_xcvr_if_pulse_adj [Array get rx_xcvr_if_pulse_adj] Rückgabe [Liste $l_RX_XCVR_IF_PULSE_ADJ $l_RX_XCVR_IF_PULSE_ADJ_SIGN] |
proc determine_rx_ref_lane {lst_rx_xcvr_if_pulse_adj VL ui rx_pcs_bitslip_cnt rx_pcs_dlpulse_aligned l_rx_apulse_offset l_rx_apulse_offset_sign l_rx_apulse_wdelay l_rx_apulse_time ip_inst_base_addr} { # # Argumente: # returns: 'array-lists' für Rx Spulse Offset (+sign bit). Rx ref pl/vl/fl
Array-Satz rx_apulse_offset $l_Rx_Apulse_Offset Array-Satz rx_apulse_offset_sign $l_Rx_Apulse_Offset_Sign Array-Satz rx_apulse_wdelay $l_rx_apulse_wdelay Array-Satz rx_apulse_time $l_rx_apulse_time Array-Satz rx_xcvr_if_pulse_adj $lst_rx_xcvr_if_pulse_adj
print_info_time "Bestimmung der RX-Referenzspur" # a) Bestimmen Sie die Offsets des Sync-Pulses (Alignment Marker) in Bezug auf den asynchronen Puls if {$::FEC > 0} { print_out "\tVariant : FEC>0" for {set fl 0} {$fl < $::FL} {incr fl} { Set fl_minus [expr $fl - [expr $fl % $::P L_FL_MAP]] set val0 [format 0x%X [expr $rx_xcvr_if_pulse_adj($fl_minus) & 0x0000001F]] set val1 [format 0x%X [expr $rx_xcvr_if_pulse_adj($fl) + $val 0]]
if {$val 1 > $rx_xcvr_if_pulse_adj($fl_minus)} { Set rx_spulse_offset_sign($fl) 0 set rx_spulse_offset_0 [format 0x%lX [expr [expr ($rx_xcvr_if_pulse_adj($fl) - $rx_xcvr_if_pulse_adj($fl_minus)) + $val 0] * $ui * $::P L_FL_MAP]] set rx_spulse_offset_1 [format 0x%lX [expr $rx_spulse_offset_0 & 0x7FFFFFFFFFF]] ; # 43'rx_spulse_offset_0 set rx_spulse_offset($fl) [format 0x%X [expr $rx_spulse_offset_1 >> [expr 28 - 16]]] } else { Satz rx_spulse_offset_sign($fl) 1 set rx_spulse_offset_0 [format 0x%lX [expr [expr ($rx_xcvr_if_pulse_adj($fl_minus) - $rx_xcvr_if_pulse_adj($fl)) - $val 0] * $ui * $::P L_FL_MAP]] set rx_spulse_offset_1 [format 0x%lX [expr $rx_spulse_offset_0 & 0x7FFFFFFFFFF]] ; # 43'rx_spulse_offset_0 set rx_spulse_offset($fl) [format 0x%X [expr $rx_spulse_offset_1 >> [expr 28 - 16]]] } |
proc determine_rx_ref_lane {lst_rx_xcvr_if_pulse_adj lst_rx_xcvr_if_pulse_adj_sign VL ui rx_pcs_bitslip_cnt rx_pcs_dlpulse_aligned l_rx_apulse_offset l_rx_apulse_offset_sign l_rx_apulse_wdelay l_rx_apulse_time ip_inst_base_addr} { # # Argumente: # returns: 'array-lists' für Rx Spulse Offset (+sign bit). Rx ref pl/vl/fl
Array-Satz rx_apulse_offset $l_Rx_Apulse_Offset Array-Satz rx_apulse_offset_sign $l_Rx_Apulse_Offset_Sign Array-Satz rx_apulse_wdelay $l_rx_apulse_wdelay Array-Satz rx_apulse_time $l_rx_apulse_time Array-Satz rx_xcvr_if_pulse_adj $lst_rx_xcvr_if_pulse_adj Array-Satz rx_xcvr_if_pulse_adj_sign $lst_rx_xcvr_if_pulse_adj_sign
print_info_time "Bestimmung der RX-Referenzspur" # a) Bestimmen Sie die Offsets des Sync-Pulses (Alignment Marker) in Bezug auf den asynchronen Puls if {$::FEC > 0} { print_out "\tVariant : FEC>0" for {set fl 0} {$fl < $::FL} {incr fl} { Set fl_minus [expr $fl - [expr $fl % $::P L_FL_MAP]] set val0 [format 0x%X [expr $rx_xcvr_if_pulse_adj($fl_minus) & 0x0000001F]] set val1 [format 0x%X [expr $rx_xcvr_if_pulse_adj($fl) + $val 0]]
if { $rx_xcvr_if_pulse_adj_sign($fl) == 1} { Satz rx_spulse_offset_sign($fl) 1 set rx_spulse_offset_0 [format 0x%lX [expr $rx_xcvr_if_pulse_adj($fl) * $ui * $::P L_FL_MAP]] set rx_spulse_offset_1 [format 0x%lX [expr $rx_spulse_offset_0 & 0x7FFFFFFFFFF]] ; # 43'rx_spulse_offset_0 set rx_spulse_offset($fl) [format 0x%X [expr $rx_spulse_offset_1 >> [expr 28 - 16]]] } else { if {$val 1 > $rx_xcvr_if_pulse_adj($fl_minus)} { Set rx_spulse_offset_sign($fl) 0 set rx_spulse_offset_0 [format 0x%lX [expr [expr ($rx_xcvr_if_pulse_adj($fl) - $rx_xcvr_if_pulse_adj($fl_minus)) + $val 0] * $ui * $::P L_FL_MAP]] set rx_spulse_offset_1 [format 0x%lX [expr $rx_spulse_offset_0 & 0x7FFFFFFFFFF]] ; # 43'rx_spulse_offset_0 set rx_spulse_offset($fl) [format 0x%X [expr $rx_spulse_offset_1 >> [expr 28 - 16]]] } else { Satz rx_spulse_offset_sign($fl) 1 set rx_spulse_offset_0 [format 0x%lX [expr [expr ($rx_xcvr_if_pulse_adj($fl_minus) - $rx_xcvr_if_pulse_adj($fl)) - $val 0] * $ui * $::P L_FL_MAP]] set rx_spulse_offset_1 [format 0x%lX [expr $rx_spulse_offset_0 & 0x7FFFFFFFFFF]] ; # 43'rx_spulse_offset_0 set rx_spulse_offset($fl) [format 0x%X [expr $rx_spulse_offset_1 >> [expr 28 - 16]]] } } |
Array-Satz rx_xcvr_if_pulse_adj [configure_rx_fec_cw_pos $inst_num $init_pl] |
if {$::FEC > 0} { Setzen Sie int_list [configure_rx_fec_cw_pos $inst_num $init_pl] $int_List-l_rx_xcvr_if_pulse_adj l_rx_xcvr_if_pulse_adj_sign zuweisen
Array-Satz rx_xcvr_if_pulse_adj $l_rx_xcvr_if_pulse_adj Array-Satz rx_xcvr_if_pulse_adj_sign $l_rx_xcvr_if_pulse_adj_sign if {$::d ebug} { for {set fl 0} {$fl < $::FL} {incr fl} { print_out "\trx_xcvr_if_pulse_adj($fl) : [Format 0x%08X $rx_xcvr_if_pulse_adj($fl)]" print_out "\trx_xcvr_if_pulse_adj_sign($fl) : [Format 0x%08X $rx_xcvr_if_pulse_adj_sign($fl)]" } } |
# Schritt 3: Bestimmen Sie die RX-Referenzspur Setzen Sie int_list [determine_rx_ref_lane [Array get rx_xcvr_if_pulse_adj]\ $VL\ |
# Schritt 3: Bestimmen Sie die RX-Referenzspur Setzen Sie int_list [determine_rx_ref_lane [Array get rx_xcvr_if_pulse_adj]\ [array get rx_xcvr_if_pulse_adj_sign]\ $VL |
- Speichern Sie die Datei
Dieses Problem wurde ab der Intel® Quartus® Prime Pro Edition Software Version 22.4 behoben.