Stefano Pellerano was born in Bari, Italy, in 1977. He received the Laurea Degree (summa cum laude) and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2000 and in 2004, respectively. During his Ph.D., his activity was focused on the design of fully integrated low-power frequency synthesizers for WLAN applications. In 2003 he has been a consultant with Agere Systems (former Bell Labs) in Allentown, PA. Since 2004 he has been with Intel Labs, in Hillsboro, OR. He is now Principal Engineer leading the Next Generation Radio Integration Lab, where he drives several research activities focused at enabling radio circuit integration in deeply-scaled CMOS technologies. His main research contributions include MIMO transceivers for WiFi, digital PLLs, high-efficient digital architectures for polar and outphasing transmitters, mm-wave radio transceiver and phased-array systems, and low-power radios. Recently, he is also exploring cryogenic CMOS integrated electronics for qubit control in fault tolerant scalable quantum computers. Stefano has authored or co-authored more than 40 IEEE conference and journal papers, one book chapter and more than 15 issued patents. He is currently serving as the Wireless Subcommittee Chair for the IEEE International Solid-State Circuit Conference (ISSCC). He served as the Technical Program Chair and General Chair for the IEEE Radio Frequency Integrated Circuit (RFIC) Symposium in 2018 and 2019 respectively and he is now part of the RFIC Executive Committee.