Moore’s Law Continues to Inspire Innovation at DARPA ERI

By Narayan Srinivasa


  • Moore’s Law continues to drive innovative research presented at the 2020 DARPA ERI Summit and MTO Symposium.

  • Today’s demand for efficient microelectronics requires integration of materials, structures, and architectures – not just transistor scaling.



Intel leaders and scientists spoke about the importance of keeping innovative semiconductor technology on pace with Moore’s Law at the 2020 DARPA Electronics Resurgence Initiative (ERI) Summit and Microsystems Technology Office (MTO) Symposium this past August.

The annual event brought together leaders from across the electronics ecosystem – spanning government, defense, academia, and industry – to foster collaboration and share technical progress on DARPA’s five-year, $1.5 billion investment in the advancement of the U.S. semiconductor industry.

Moore’s Law inspired DARPA to support research on advanced new materials, circuit design tools, and system architectures to continue the expansion of microelectronics technology. In 1965, Intel co-founder Gordon Moore made a prediction that would set the pace for the modern digital revolution: the number of transistors incorporated in a chip will approximately double every 24 months. From careful observation of this emerging trend, Moore extrapolated that computing would dramatically increase in power, and decrease in relative cost, at an exponential pace.

Known as Moore's Law, this forecast for the pace of silicon technology essentially described the basic business model for the semiconductor industry. In his groundbreaking paper, Moore wrote that “it may prove more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” This idea encouraged DARPA to create ERI to invest in innovative semiconductor research.

“Since my 1965 paper that ERI references, what has actually happened in the intervening 52 years is far beyond anything I contemplated. It is a testimony to the creativity of many engineers and scientists that the industry has surmounted apparent roadblocks that looked to be the end of transistor scaling,” Moore wrote in 2017 in response to the launch of ERI.

Today’s demand for efficient microelectronics requires integration of materials, structures, and architectures together – not just transistor scaling, according to Dr. Michael C. Mayberry, chief technology officer at Intel. Mayberry spoke about the importance of continuing Moore’s law to advance the semiconductor industry during a Technical Leadership Panel with other semiconductor industry leaders from Texas Instruments, Raytheon Intelligence & Space, Qorvo, and SEMI Americas at the ERI Summit.

“Like other times in the history of Moore’s Law, power scaling challenges are back. We see 2D scaling slowing, but 3D scaling is now becoming possible. Novel kinds of technology beyond CMOS devices and heterogenous architectures will be needed to advance the field,” said Mayberry, who is also senior vice president and general manager of Technology Development, where he is responsible for the research, development and deployment of next-generation silicon logic, packaging, and test technologies.

Next-generation platforms increasingly require innovative solutions that provide significantly higher performance, lower power, and smaller form factors. The explosion in data center capabilities and proliferation of IoT technologies are emerging as key drivers. In addition, advancements in terabit networking, optical transport, 8K video, and 5G wireless domains are ramping up rapidly, pushing the semiconductor industry to find innovative solutions.

3D heterogeneous integration

To meet this demand, technology such as 3D heterogeneous integration is promising for advancing the microelectronics field, according to the ERI Summit presentation on “The Next Dimensions in Heterogeneous Integration: Nano-, Micro-, and Macro-3D ICs” by Intel’s Paul Fischer, research team leader in Technology Development, and Farhana Sheikh, senior staff scientist in the Programmable Solutions Group.

Heterogeneous integration 3D system-in-package (SiP) technology enables next-generation platforms by offering higher bandwidth, lower power, a smaller form factor, and increased functionality and flexibility. This solution combines the right mix of functionality on the right process nodes to provide system functionality in a single package. The heterogeneous 3D SiP technology enables in-package integration of a range of components such as analog, memory, ASIC, and CPU. It also integrates transceiver die or tiles from different process nodes in the same package.

According to Moore’s Law, the successful realization of phased-array antenna systems will include using multiple “integrated microwave power resources that would revolutionize radar.” Intel’s research into 3D heterogeneous integration has revealed both challenges and opportunities as they apply to high-frequency phased array systems operating at millimeter (mm-W) and terahertz (THz) frequencies. Intel researchers are focusing on 3D integration at the nano, micro, and macro level, and creating new types of platforms to address emerging applications.

Silicon photonics

At the ERI Summit, Intel also shared its continuing work to make optical I/O with silicon photonics a reality. Silicon photonics combines a silicon integrated circuit with a semiconductor laser, enabling faster data transfer over longer distances compared to traditional electronics. In a presentation entitled “Future Architectures with Photonics,” senior principal engineer Josh Fryman explored how to change architectures and systems to enable a package-to-package silicon photonic link at low latency and high bandwidth, with better energy efficiency than electrical I/O. Ultimately, this technology will be necessary for bandwidth scalability in future networks.

From the past to the future

Consumer demand has driven the global semiconductor market for more than 50 years. Industry drivers have shifted from national security in the late 1960s, to business computing in the 1970s, to commercial computing in the 1980s, to mobile and smartphones in the 2000s, to Internet of Things (IoT) devices in the 2010s, and now to the cloud. Major consumer trends such as artificial intelligence, computing in the cloud, 5G and beyond wireless technologies, and computing at the edge will influence microelectronics development over the next 10 years. The need to develop scalable, secure, and efficient computing technologies from the edge to the cloud will drive the semiconductor market to address these trends.

“Latency, bandwidth, and compute need to be equally supported in today’s computing system but advances in compute are proceeding at a faster pace than advances in bandwidth and latency improvements,” said Mayberry. “Distributed compute becomes key and the need to compute more locally to get more balance between these three parameters is needed to support the new demands of today and the future.”