IP Cores IP Catalog and Parameter Editor Altera FPGA IP Cores/LPM Clear Box Command-Line Tool altsquare Altera IP altstratixii_oct Altera IP altsyncram Altera IP altufm_i2c Altera IP altufm_none Altera IP altufm_osc Altera IP altufm_parallel Altera IP altufm_spi Altera IP altasmi_parallel Altera IP csdpram Altera IP csfifo Altera IP divide Altera IP lpm_and Altera IP lpm_bustri Altera IP lpm_clshift Altera IP lpm_constant Altera IP lpm_decode Altera IP lpm_dff Altera IP lpm_ff Altera IP lpm_inv Altera IP lpm_latch Altera IP lpm_mux, mux and busmux Altera IP lpm_or Altera IP lpm_ram_dp Altera IP lpm_ram_dq Altera IP lpm_ram_io Altera IP lpm_rom Altera IP lpm_shiftreg Altera IP lpm_tff Altera IP lpm_xor Altera IP Macrofunctions sld_signaltap IP Core Virtual JTAG Interface (VJI) Altera IP Provides access to the device through the JTAG interface. altera_soft_core_jtag_io Altera IP Generating a Netlist for Third-Party Synthesis Tools from Megafunctions and Altera IP Functions Clock Enable Signal Equalizer Control Pre-emphasis Control Signal Altera-Specific Parameters "UNUSED" Parameter Value WYSIWYG Atom Names Unavailable for Use as Altera IP Instance Names Example of Pipeline Stages in the Divide Function Example of Using the Full Output as an Extra Bit for the usedw[ ] Output alt3pram Altera IP altgx Altera IP alt_oct IP Core altclklock IP Core altdll Altera IP RAM: 2-PORT Altera IP Parameterized dual-port RAM Altera® IP. altdq Altera IP altdq_dqs Altera IP altdqs Altera IP altmem_init Altera IP ALTMEMPHY Altera IP altotp Altera IP altserial_flash_loader Altera IP altsource_probe Altera IP