IP Catalog and Parameter Editor

The Quartus^® Prime software supports easy customization and integration of IP cores into your project. Use the IP Catalog and parameter editor GUIs to customize IP cores and generate files representing your custom IP variation.

The IP Catalog displays the installed IP cores available for your design. Double-click any IP core to launch the parameter editor and generate files representing your IP variation. Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.
• Type in the Search field to locate any full or partial IP core name in IP Catalog.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and click links to IP documentation.
• Click Search for Partner IP to access partner IP information on the web.

The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Platform Designer system file (.qsys) or Quartus^® Prime IP file (.qip) representing the IP core in your project. You can also parameterize an IP variation without an open project.

The IP Catalog is also available in Platform Designer (View > IP Catalog). The Platform Designer IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus^® Prime IP Catalog.

The parameter editor helps you to configure your IP variation ports, parameters, architecture features, and output file generation options. Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values for specific applications. View port and parameter descriptions and links to detailed documentation in the parameter editor. Generate testbench systems or example designs (where provided) from the parameter editor.

To modify one of your existing IP core variations, perform one of the following:

• Click File > Open and select the top-level HDL(.v, or .vhd) IP variation file to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes.
• Click View > Utility Windows > Project Navigator > IP Components and double-click the IP variation to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes.

A selection of Altera IP cores also include example designs that you can use or modify to replicate similar functionality in your own system. You must generate the example design HDL from the parameter editor before you can view or use the example.

The Example Design icon identifies cores that have example designs available for generation:

If present, click the Example Design button in the parameter editor to generate the example design. Otherwise, click Generate > Generate Example Design.

You can also access this command in Platform Designer by clicking Generate > Generate Example Design in Platform Designer parameter editor. You can add designs to the Example Designs list with the following Tcl command:

add_fileset my_example EXAMPLE_DESIGN "" "My Platform Designer Example"

This command adds the example design to the Example Designs list that appears when you point to the Generate Example Design command. Platform Designer creates a directory adjacent to the .qsys file, as follows:

<instance name> - My Platform Designer Example
<instance name>_my_example