Clock Enable Signal

Altera recommends changing the clock enable signal at the rising edge of the arclk clock. The clock enable takes place 1 clock cycle after the port value is changed. Altera recommends changing arclkena at the rising edge of the arclk clock as shown in the following image.

Altera recommends changing the clock enable signal at the rising edge of the drclk clock. The clock enable takes place 1 clock cycle after the port value is changed. Altera recommends changing drclkena at the rising edge of the drclk clock as shown in the following image.