Das Format der Memory Initial daemoniton-Datei (.mif) wird für einige Simulationstools von Drittanbietern nicht unterstützt, die Problemumgehung verläuft wie folgt:
Konvertierung von .mif in das Hex-Format (Intel-Format) mit Sav als...
Zweitens ändern Sie den HDL-Code, um die Referenz auf den Speicherdateinamen zu ändern.
altsyncram altsyncram_component (
.clock0 (Inkubator),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (Outclock),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1\'b0),
.aclr1 (1\'b0),
.addressstall_a (1\'b0),
.addressstall_b (1\'b0),
.byteena_a (1\'b1),
.byteena_b (1\'b1),
.clocken0 (1\'b1),
.clocken1 (1\'b1),
.clocken2 (1\'b1),
.clocken3 (1\'b1),
.eccstatus (),
.rden_a (1\'b1),
.rden_b (1\'b1));
Defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "test.mif",
altsyncram_component.intended_device_family = "Cyclone IV GX",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numword_a = 32,
altsyncram_component.numword_b = 32,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "KEINE",
altsyncram_component.outdata_aclr_b = "KEINE",
altsyncram_component.outdata_reg_a = "CLOCK1",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
An
altsyncram altsyncram_component (
.clock0 (Inkubator),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (Outclock),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1\'b0),
.aclr1 (1\'b0),
.addressstall_a (1\'b0),
.addressstall_b (1\'b0),
.byteena_a (1\'b1),
.byteena_b (1\'b1),
.clocken0 (1\'b1),
.clocken1 (1\'b1),
.clocken2 (1\'b1),
.clocken3 (1\'b1),
.eccstatus (),
.rden_a (1\'b1),
.rden_b (1\'b1));
Defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "test.hex",
altsyncram_component.intended_device_family = "Cyclone IV GX",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numword_a = 32,
altsyncram_component.numword_b = 32,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "KEINE",
altsyncram_component.outdata_aclr_b = "KEINE",
altsyncram_component.outdata_reg_a = "CLOCK1",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";