Kritisches Problem
Die folgenden Intel® FPGA IP Kerne generieren Beispieldesigns für das Transceiver SoC Development Kit der Intel Agilex® 7 FPGA-Reihe mit falschen VID-Einstellungen.
1) Serial Lite IV Intel® FPGA IP
2) Interlaken (2. Generation) Intel® FPGA IP
3) Triple-Speed-Ethernet Intel® FPGA IP
4) Dynamische E-Tile Rekonfiguration Intel® FPGA IP
5) E-Tile Hard IP für Ethernet und CPRI PHY Intel® FPGA IP
6) JESD204B Intel® FPGA IP
7) JESD204C Intel® FPGA IP
8) Ethernet-Subsystem-Intel® FPGA IP
Die korrekten VID-Einstellungen finden Sie in Abschnitt 6.1 Hinzufügen von SmartVID-Einstellungen in der Intel® Quartus® Prime QSF-Datei des Intel Agilex® F-Series Transceiver-SoC Development Kit Benutzerhandbuchs.
Aktualisieren Sie die Designbeispiele mit den richtigen VID-Einstellungen , wie unten gezeigt:
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
set_global_assignment -name USE_CONF_DONE SDM_IO16
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEARES FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
Dieses Problem soll in einer zukünftigen Version der Intel® Quartus® Prime Pro Edition-Software behoben werden.