Warum wird mein Cyclone V- oder Stratix V Altera_PLL-Reset-Port in der Simulation invertiert?

Um dieses Problem in ModelSim zu umgehen, fügen Sie den folgenden Switch zum Befehl vlog hinzu

definieren POSTFIT_SIM_USE_ICD_PLL_MODEL

Fügen Sie beispielsweise die folgenden Zeilen zur Datei *_run_msim_gate_verilog.do hinzu

Für Cyclone V-Designs

vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL /quartus/eda/sim_lib/mentor/cyclonev_*.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL /quartus/eda/sim_lib/cyclonev_atoms.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL

Für Stratix V-Designs

vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL /quartus/eda/sim_lib/mentor/stratixv_*.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL /quartus/eda/sim_lib/stratixv_atoms.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL

/quartus/eda/sim_lib/altera_primitives.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL /quartus/eda/sim_lib/altera_lnsim.sv
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL /quartus/eda/sim_lib/220model.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL /quartus/eda/sim_lib/sgate.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL /quartus/eda/sim_lib/altera_mf.v
vsim  -t 1ps transport_int_delays transport_path_delays -voptargs= acc gate_work.