ID:24289 For MIPI design, review "MIPI D-PHY Placement Rules" as outlined in the Intel Agilex 5 FPGA MIPI D-PHY IP User Guide.

CAUSE: The design violates Intel Agilex 5 placement restriction on DPHY and LVCMOS I/O standards.

ACTION: Review the MIPI D-PHY Placement Rules in the Intel Agilex 5 FPGA MIPI D-PHY IP User Guide and add pin location assignment.