ID:24313 For MIPI design, review "Using the Remaining I/O Pin from Same Byte Location" as outlined in the Intel Agilex 5 FPGA MIPI D-PHY IP User Guide.

CAUSE: The design violates Intel Agilex 5 MIPI Byte I/O Standard restriction.

ACTION: Review the Using the Remaining I/O Pin from Same Byte Location in the Intel Agilex 5 FPGA MIPI D-PHY IP User Guide.