ID:24290 For LVDS SERDES design, review "Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank" as outlined in the Intel Agilex 5 General-Purpose I/O User Guide.

CAUSE: The design violates Intel Agilex 5 placement restriction on LVDS and LVCMOS I/O standards.

ACTION: Review the Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank in the Intel Agilex 5 General-Purpose I/O User Guide and add pin location assignment.