LNT-50006: DSP Control Signal Registers Reset Mode Mismatch
Description
DSP control signals (CE/RST) are driven by flops with async/sync clear types that don't match the DSP's clear mode. This condition prevents any further register packing.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| DSP_Chain_Threshold | Chain-length threshold for unregistered DSP chain connections | integer | 2 | 1 | |
| DSP_Check_User_WYSIWYGs | Check directly instantiated DSPs | bool | True |
Recommendation
Ensure that all registers feeding and fed by the DSP (inputs, ctrl signals, outputs), that you intend to pack, share the same reset type (ASYNC or SYNC).
Severity
Low
Tags
| Tag | Description |
|---|---|
| dsp | Design rule checks related to DSP blocks inside the FPGA fabric. |
| reset-usage | Design rule checks related to safe resets or appropriate use of reset modes. |
Device Family
- Agilex®
- Agilex®
- Agilex®
- Stratix® 10