ID:22489 Ignoring line for bad VHDL conditional analysis variable definition (<line>)
CAUSE: The VHDL conditional analysis variable definition was malformed.
ACTION: Use the expected syntax for VHDL conditional analysis variable definitions.
| List of Messages | Parent topic: List of Messages |
CAUSE: The VHDL conditional analysis variable definition was malformed.
ACTION: Use the expected syntax for VHDL conditional analysis variable definitions.