ID:21969 All shift registers are inferred to RAM. This can lead to formal verification failure.

CAUSE: You attempted to run formal verification when all shift registers are packed. That leads to no register before or after the inferred RAM and formal verification may fail.

ACTION: If you prefer to run formal verification without physical synthesis, add the following variables in the Quartus Prime Settings File (.qsf): SHIFT_REGISTER_DO_NOT_LEAVE_REGISTER_OUTSIDE = ON.