ID:335097 The Timing Analyzer is analyzing <number of latches> registers as latches. For more details, view the "User-Specified and Inferred Latches" table in the Synthesis report.

CAUSE: The specified nodes are registers that use asynchronous load and data signals to implement a latch. These nodes are treated as latches during timing analysis, using the asynchronous load as the latch enable, and the asynchronous data as the data input for the latch. For a listing of these nodes, refer to the \"User-Specified and Inferred Latches\" table in the Synthesis report."

ACTION: No action is required.