ID:22793 The Timing Analyzer is analyzing <number of latches> combinational loops as latches. To see the list of latches that were not entered as explicit comb loops in design files, view the "User-Specified and Inferred Latches" table in the Synthesis report.

CAUSE: The Timing Analyzer found latches implemented using look-up tables (LUTs) with combinational feedback. Most properly entered latches still end up implemented with LUTs. The Timing Analyzer replaces the combinational loop with an equivalent latch. The Timing Analyzer treats this logic as a synchronous endpoint, and will not analyze the path through the node.

ACTION: No action is needed. A combinational loop might have been inferred due to mistakes in the design entry, but these loops likely do not have any clock defined for their enable signal. The enable signals with undefined clocks will trigger a separate warning.