ID:22881 RAM logic "<name>" is uninferred due to the RAM's dataout registers are powered up to high

CAUSE: You specified dataout registers of RAM in a Verilog Design File (.v) or VHDL Design File (.vhd) as powered up to high. However, Analysis & Synthesis cannot implement RAM hardware because RAM's internal registers cannot be powered up to high .

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, ensure that the RAM's dataout registers are not powered up to high.