ID:13369 Verilog HDL Loop Statement error at <location>: loop with non-constant loop condition not supported for <loop type>

CAUSE: In a loop statement at the specified location in a Verilog Design File (.v), you specified a loop condition that does not evaluate to constant true or false on each loop iteration. For example, it may depend on an input to your module.

ACTION: Modify the loop condition so that it evaluates to a constant true or false. You can also use a disable (Verilog) or break statement (SystemVerilog).