ID:22768 Cannot synthesize true dual-port RAM logic "<name>". This RAM is set to read-during-write mixed-port mode with the old-data parameter enabled, which is not supported by the selected device family.

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified logic that acts as a true dual port RAM with read-during-write mixed-port mode with the old-data parameter enabled, but the selected device family does not support this.

ACTION: Either change the RAM to not be true dual port or change the mixed-port read-during-write mode.