ID:22556 Cannot synthesize dual-clock dual-port RAM logic "<name>". This RAM logic configuration is not supported by the selected device family, but you may configure RAM: 2-PORT Intel FPGA IP to emulate TDP dual clock mode through Platform Designer.

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified logic that acts as a true dual port RAM with dual clocks, but the selected device family does not support this.

ACTION: Through Platform Designer, RAM: 2-PORT Intel FPGA IP can be configured to emulate TDP dual clock mode.