ID:20083 Second pipeline registers for DSP block WYSIWYG primitive "<atom name>" can be enabled only under one of the following conditions: An input register is used; Neither the pre-adder feature or the internal coefficient feature are not used but both an input register and an output register are used; An input register and an input pipeline register are used; An input register, an input pipeline register, and an output register are used.

CAUSE: Illegal clock enable parameter configuration of second pipeline registers for the specified DSP block WYSIWYG primitive"

ACTION: Correct the clock enable parameter of the specified second pipeline register.