Input Ports

address[]

Yes

Address input to the memory.

Input port LPM_WIDTHAD wide. If memenab is used, it should be inactive when address[] is changing.

we

Yes

Write Enable input. Enables write operations to the memory when high.

If no Clock ports are used, the data on the address[] port should not change when we is high (1). Required if clock is not present.

inclock

No

Synchronizes loading memory.

If the inclock port is used, the we port acts as an enable for write operations synchronized to the rising edge of the inclock signal. If the inclock port is not used, the we port acts as an enable for asynchronous write operations.

outclock

No

Synchronizes dio[] from memory.

The addressed memory content-to-q[] response is synchronous when the outclock port is connected, and asynchronous when it is not connected.

memenab

No

Memory output tri-state enable.

Either memenab or outenab must be connected. If memenab is present, it should be inactive when address[] is changing. This port is available for backward compatibility only and Intel recommends that you not use this port.

outenab

No

Output Enable input. High (1): dio from Memory [address] Low (0): Memory [address] from dio.

Either memenab or outenab must be present.