DisplayPort Intel® FPGA IP Core

Take a 2-minute tour to see where the latest connectivity standards show up!

What's New - DisplayPort IP v1.4

Intel is an early entrant into the market with a fully VESA-compliant DisplayPort Intel® FPGA IP core v1.4. The DisplayPort IP core has the following features:
  • Support for HBR3 and a total 32.4 Gbps bandwidth – 8.1 Gbps per lane
  • Future Display Stream Compression (DSC) to make 8k60 possible
  • Plug and play with other Intel video intellectual property (IP) cores

Start Developing with the DisplayPort Intel FPGA IP Core Now!

DisplayPort is a high-speed serial interface standard for video and audio supported by industry leaders in broadcast, consumer, medical, industrial, and military applications. It is primarily used to connect video sources to display devices like computer monitors.

The DisplayPort Intel FPGA IP core has the following advantages:

  • Higher bandwidth with DisplayPort v1.4 
  • Royalty-free standard
  • Data transmission on all four lanes
  • Latching cable to physically secure connection
  • Multi-Stream Transport to run multiple monitors from a single cable

The VESA-certified DisplayPort Intel FPGA IP core implements a receiver and transmitter per lane with 1, 2, or 4 differential data lanes at 1.62, 2.7, 5.4, or 8.1 Gbps. High-bandwidth Digital Content Protection (HDCP)-encrypted transmission and future DSC can also be integrated into our IP through one of Intel's partners. For more information, contact Bitec.

DisplayPort IP Core Connection Diagram

IP Core Feature


Scalable main data link

  • 1, 2 or 4 lane operation
  • 1.62, 2.7 , 5.4 or 8.1 Gbps per lane with an embedded clock

Color support

  • RGB 18, 24, 30, 36 or 48 bits per pixel (bpp) color depths
  • YCbCr 4:4:4 24, 30, 36 or 48 bpp color depths
  • YCbCr 4:2:2 16, 20, 24 or 32 bpp color depths
  • YCbCr 4:2:0 12, 15, 18 or 24 bpp color depths

Transceiver data interface

40 bit (quad symbol) or 20 bit (dual symbol)

Pixels per clock

1, 2 or 4 pixels per clock


2 or 8 channels of embedded audio

Multistream transfer

1 to 4 source and sink video streams


20 bit mode

Maximum Link Rate

40 bit mode

Maximum Link Rate


Cyclone® V

2.7 Gbps

2.7 Gbps


Arria® V GX

2.7 Gbps

5.4 Gbps


Arria V GZ

5.4 Gbps

5.4 Gbps


Stratix® V

5.4 Gbps

5.4 Gbps


Intel Arria 10

5.4 Gbps Max.

8.1 Gbps Max.


5.4 Gbps/8.1 Gbps


Year IP was first released


Latest version of Intel Quartus® Prime design software supported





Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file

  • Yes
  • Yes
  • Yes
  • Yes
  • Yes
  • No

Any additional customer deliverables provided with IP


Parameterization GUI allowing end user to configure IP


IP core is enabled for the Intel FPGA IP Evaluation Mode Support


Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided


Driver operating system (OS) support



User interface

Other (Video Data)

IP-XACT metadata



Simulators supported

ModelSim, VCS, Riviera-PRO, NCSim

Hardware validated

Intel Arria 10, Arria V GX, Arria V GZ, Cyclone V, Stratix V

Industry standard compliance testing performed


If Yes, which test(s)?

VESA DisplayPort Link Layer CTS

If Yes, on which Intel FPGA device(s)?

Arria V, Intel Arria 10

If No, is it planned?



IP has undergone interoperability testing


If yes, on which Intel FPGA device(s)

Arria V, Stratix V, Intel Arria 10, Cyclone V

Interoperability reports available

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Development Kits

The following development kits and daughtercards are available from Intel and Intel partners for you to get started on your DisplayPort designs. 

Design Examples

The following design examples are available for you to run on the development kits. Their block diagrams are shown below.

Hardware Demonstration Block Diagram
UHD Scaler and Mixer Design Example
DisplayPort and Video and Image Processing Suite Design Example (TX Only)
DisplayPort and Video and Image Processing Suite Design Example (TX-RX)

Additional support for this IP core is available from Intel Premier Support. You can also refer to the following documentation: