PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 1/12/2024
Public
Document Table of Contents

1. About the PHY Lite for Parallel Interfaces IP

Updated for:
Intel® Quartus® Prime Design Suite 23.4

This user guide describes the following IPs:

  • PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2)
  • PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20)
  • PHY Lite for Parallel Interfaces Intel® Stratix® 10 Intel® FPGA IP
  • PHY Lite for Parallel Interfaces Intel® Arria® 10 Intel® FPGA IP
  • PHY Lite for Parallel Interfaces Intel® Cyclone® 10 GX Intel® FPGA IP

You can primarily use the PHY Lite for Parallel Interfaces IPs for building custom memory interface PHY blocks. You can use this solution to interface with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (synchronous mode), and mobile DDR. The PHY Lite for Parallel Interfaces Intel® FPGA IP is suitable for simple parallel interfaces.

The IPs have a dedicated PHY clock tree in each I/O bank. The PHY clock tree is short that yields lower jitter and duty cycle distortion (DCD), enabling designs to achieve higher performance. This IP controls the strobe-based capture I/O elements. Each instance of the IP can support interfaces of data/strobe capture groups.

In addition, this IP supports the Dynamic Reconfiguration feature, which enables reconfiguration of the data and strobe delays. You can align the data and strobe through calibration to achieve timing closure at high frequencies.