Intel® Stratix® 10 SoCs, combine a quad-core ARM* Cortex*–A53 MPCore* hard processor system with the revolutionary Intel® Hyperflex™ FPGA Architecture to deliver the embedded performance, power efficiency, density, and system integration necessary for embedded applications.
Intel® Stratix® 10 SoCs empowers the USR in the ARM* ecosystem. ARM's next-generation 64-bit architecture (ARMv8) enabling enable hardware virtualization, system management and monitoring capabilities, and acceleration pre-processing. The ARM* Cortex-A53* processor supports 32-bit execution mode and board support packages for popular operating system including Linux*, Wind River’s VxWorks*, Micrium’s uC/OS-II* and uC/OS-III*, and more.
New engine optimized for multi-million logic elements (LE) FPGA designs providing significant reduction in design iterations, Intel® Stratix® 10 SoC Virtual Platform to enable early software development and verification, and C-based design entry using the Intel® FPGA SDK for OpenCL™, offering a design environment that is easy to implement on SoC FPGAs. Heterogeneous debug, profiling, and whole chip visualization with Intel® FPGA SoC FPGA Embedded Development Suite (EDS) featuring the ARM* Development Studio 5* (DS-5*) Intel® SoC FPGA Edition Toolkit.
HPS: Quad-core ARM* Cortex*-A53 Hard Processor System
SDM: Secure Device Manager
EMIB: Embedded Multi-Die Interconnect Bridge
Feature |
Description |
|---|---|
Processor |
Quad-core ARM* Cortex*–A53 MPCore* processor cluster up to 1.5 GHz |
Coprocessors |
Vector floating-point unit (VFPU) single and double precision, ARM* Neon* media processing engine for each processor |
Level 1 Cache |
32 KB L1 instruction cache with parity, 32 KB L1 data cache with error correction code (ECC) |
Level 2 Cache |
1 MB KB shared L2 cache with ECC |
On-Chip Memory |
256 KB on-chip RAM |
System Memory Management Unit |
System Memory Management Unit enables a unified memory model and extends hardware virtualization into peripherals implemented in the FPGA fabric |
Cache Coherency Unit |
Provides one-way (I/O) coherency that allows a CCU master to view the coherent memory of the ARM* Cortex*–A53 MPCore* CPUs |
Direct Memory Access (DMA) Controller |
8-channel direct memory access (DMA) |
Ethernet Media Access Controller (EMAC) |
3X 10/100/1000 EMAC with integrated DMA |
USB On-The-Go Controller (OTG) |
2X USB OTG with integrated DMA |
UART Controller |
2X UART 16550 compatible |
Serial Peripheral Interface (SPI) Controller |
4X SPI |
I2C Controller |
5X I2C |
SD/SDIO/MMC Controller |
1X eMMC 4.5 with DMA and CE-ATA support |
NAND Flash Controller |
1X ONFI 1.0 or later 8 and 16-bit support |
General-Purpose I/O (GPIO) |
Maximum 48 software-programmable GPIO |
| Timers | 4X general-purpose timers, 4X watchdog timers |
| System Manager | Contains memory-mapped control and status registers and logic to control system-level functions and other HPS modules |
| Reset Manager | Resets signals based on reset requests from sources in the HPS and FPGA fabric, and software writing to the module reset control registers |
| Clock Manager | Provides software-programmable clock control to configure all clocks generated in the HPS |
Intel® Enpirion® Power Solutions are high-frequency DC-DC step-down power converters designed and validated for Intel® FPGA, CPLD, and SoCs. These robust, easy-to-use power modules integrate nearly all of the components needed to build a power supply – saving you board space and simplifying the design process.
Browse through the development tools available for building software and creating FPGA designs for Intel® SoC FPGAs.
Intel® SoC FPGAs are ARM* processor-based and inherit the strength of the ARM* eco-system. Intel, our ecosystem partners, and the Intel® SoC FPGA user community provide a wide range of options to meet your SoC FPGA development needs.
In this video, we look at the unique transceiver architecture of Intel® Stratix® 10 FPGAs. See H-Tile transceivers that are connected via Intel's EMIB technology and operating at 28 Gbps backplane performance.
Intel® Hyperflex™ FPGA Architecture in Intel® Stratix® 10 devices provides 2X the Fmax performance.1 This video shows a side-by-side comparison of an original design and a Hyper-Optimized design.
Intel® Stratix® 10 devices, which include PCI Express* (PCIe*) and memory controller hard intellectual property (IP) blocks, combined with Avalon® memory-mapped interface and direct memory access (DMA) functions to create a high-performance reference design.
Find technical documentation, videos, and training courses for your Intel® Stratix® 10 device.
Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Intel® Quartus® Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to Intel® Hyperflex™ FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users will achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.de/benchmarks.