Intel® Arria® 10 SOC FPGAs Features

Intel® Arria® 10 SoCs, based on TSMC’s 20 nm process technology, combine a feature-rich dual-core ARM* Cortex*-A9 MPCore* hard processor system (HPS) with industry-leading programmable logic technology. The Arria 10 SoCs offer a processor with rich feature set of embedded peripherals, hardened floating-point variable-precision digital signal processing (DSP) blocks, high-speed transceivers, hard memory controllers, Secure boot capability, using Elliptic Curve Digital Signature Algorithm (ECDSA) and Advanced Encryption Standard (AES), and protocol intellectual property (IP) controllers all in a single highly integrated package.

Block Diagram

Hard Processor System (HPS)

Intel® Arria® 10 SoCs feature a second-generation dual-core ARM* Cortex*-A9 MPCore* processor-based hard processor system (HPS) that is faster, more secure, and software compatible with previous-generation SoCs. With Arria 10 SoCs you can reduce board size while increasing performance by integrating a GHz-class processor, FPGA logic, and digital signal processing (DSP) functions into a single user-customizable system on a chip. Arria 10 SoCs offer the broadest selection of FPGA logic densities to date. These improvements address the performance, power, and security requirements of next-generation communications, broadcast, and computer and storage equipment.

  • Faster: At 1.5 GHz, the processor provides more than 50% increase in performance over the previous generation with 30% power reduction
  • More secure: Arria 10 SoCs support secure boot with authentication based on Elliptical Curve Digital Signature Authentication (EC DSA), with a layered public key infrastructure for root of trust support, Advanced Encryption Standard (AES) and new anti-tamper features
  • Improved architecture: Arria 10 HPS now has three Ethernet MAC cores, 256 KB Scratch-RAM, supports 8 and 16 bit NAND flash devices, eMMC SD/SDIO/MMC cards, and 72 bit DDR3/4 memory

Intel® Arria® 10 SoC Family HPS Features

The HPS is common to all the devices in the Intel® Arria® 10 SoC series.

Feature Description


Dual-core ARM Cortex-A9 MPCore processor with ARM CoreSight* debug and trace technology


Vector floating-point unit (VFPU) single and double precision, ARM NEON* media processing engine for each processor snoop control unit (SCU), acceleration coherency port (ACP)

Level 1 cache 32 KB L1 instruction cache, 32 KB L1 data cache
Level 2 cache 512 KB shared L2 cache
Scratch pad RAM 256 KB
HPS DDR memory DDR4 and DDR3 (up to 64 bit with error correction code (ECC))
Direct memory access (DMA) controller 8-channel direct memory access (DMA)
Ethernet media access controller (EMAC) 3 x 10/100/1000 EMAC with integrated DMA
USB On-The-Go controller (OTG) 2x USB OTG with integrated DMA
UART controller 2x UART 16550 compatible
Serial peripheral interface (SPI) controller 4x SPI
I2C controller 5x I2C
QSPI flash controller 1x SIO, DIO, QIO SPI flash supported
SD/SDIO/MMC controller 1x eMMC 4.5 with DMA and CE-ATA support
NAND flash controller 1x ONFI 1.0 or later 8 and 16 bit support
General-purpose I/O (GPIO) Maximum 62 software-programmable GPIO
Timers 7X general-purpose timers, 4X watchdog timers
Security Secure boot, Advanced Encryption Standard (AES) and authentication based on Elliptic Curve Digital Signature Algorithm (ECDSA)
  • Dual-core ARM Cortex-A9 MPCore processor unit
    •  2.5 MIPS/MHz instruction efficiency
    • CPU frequency 1.2 GHz with 1.5 GHz via overdrive
      • At 1.5 GHz total performance of 7500 MIPS
    • ARMv7-A architecture
    • Runs 32 bit ARM instructions
      • 16 bit and 32 bit thumb instructions for 30% reduction in memory footprint
      • Jazelle* RCT execution architecture with 8 bit Java bytecodes
      • Superscalar, variable length, out-of-order pipeline with dynamic branch prediction
    • ARM NEON* media processing engine
    • Single- and double-precision floating-point unit
    • CoreSight* debug and program trace module (PTM)
    • TrustZone for security applications
    • Snoop control unit (SCU) and acceleration coherency port (ACP)
  • Cache
    • L1 cache
      • 32 KB of instruction cache
      • 32 KB of L1 data cache
      • Parity checking
    • L2 cache
      • 512 KB shared
      • 8-way set associative
      • Single event upset (SEU) protection with parity on TAG ram and error correction code (ECC) on data RAM
      • Cache lockdown support
  • On-Chip Memory
    •  256 KB of scratch on-chip RAM
    • 64 KB on-chip ROM
  • External Memory Interface
    •  Hard memory controller with support for DDR4 and DDR3
      • 40 bit (32 + 8 bit ECC) with select packages supporting 72-bit (64 bit + 8 bit ECC)
      • Support for up to 2,400 Mbps DDR4 and 2,166 Mbps DDR3 frequencies
      • ECC support including calculation, error correction, write-back correction and error counters
      • Software configurable priority scheduling on individual SDRAM bursts ECC
      • Fully programmable timing parameter support for all JEDEC specified timing parameters
      • AXI* quality of service (QoS) support for interface to logic core
      • Multiport front-end (MPFE) scheduler interface to HMC allows port sharing of HMC between CPU and logic core
    • Quad serial peripheral interface (quad SPI) flash controller
      • Single I/O (SIO), dual I/O (DIO), quad I/O (QIO) SPI flash support
      • Support for up to 108 MHz for flash frequency
    • NAND flash controller
      • ONFI 1.0 or later
      • Integrated descriptor based with direct memory access (DMA)
      • New command DMA to offload CPU for fast power down recovery
      • Programmable hardware ECC support
      • Updated to support 8 and 16 bit Flash devices
      • Support for 50 MHz flash frequency
    • Secure Digital SD/SDIO/MMC controller
      • eMMC 4.5
      • Integrated descriptor-based DMA
      • CE-ATA digital commands supported
      • 50 MHz operating frequency
    • DMA controller
      • 8-channel
      • Supports up to 32 peripheral handshake interface
  • Communication Interface Controllers
    •  3X 10/100/1000 Ethernet media access control (MAC) with integrated DMA
      • Supports RGMII and RMII external PHY Interfaces
      • Option to support other PHY interfaces through FPGA logic
        • GMII and SGMII
      • Supports IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization
      • Supports IEEE 802.1Q VLAN tag detection for reception frames
      • Supports Ethernet AVB standard
    • 2X USB On-The-Go (OTG) controller with DMA
      • Dual-Role Device (device and host functions)
        • High-speed (480 Mbps)
        • Full-speed (12 Mbps)
        • Low-speed (1.5 Mbps)
        • Integrated descriptor-based scatter-gather DMA
        • Support for external ULPI PHY
        • Up to 16 bidirectional endpoints, including control endpoint
        • Up to 16 host channels
        • Supports generic root hub
        • Configurable to OTG 1.3 and OTG 2.0 modes
        • Compatible with USB 1.1 (full-speed and low-speed)
      • 5X I2C controller (Three can be used by EMAC for MIO to external PHY)
        • Support both 100 Kbps and 400 Kbps modes
        • Support both 7 bit and 10 bit addressing modes
        • Support master and slave operating mode
      • 2X UART 16550 compatible
        • Support IrDA 1.0 SIR mode
        • Programmable baud rate up to 115.2 Kbaud
      • 4X serial peripheral interface (SPI) (2 master, 2 slaves)
        • Full and half duplex
  • Timers and I/O
    •  Timers
      • 7X general-purpose timers
      • 4X watchdog timers
    • 62 programmable general-purpose I/O (GPIO)
      • Three modules 24, 24, and 14
    • 48 I/O direct share I/O allows HPS peripherals to connect directly to I/O
  • Security
    •  Anti-tamper, secure boot, AES and authentication (SHA)
  • Interconnect to Logic Core
    •  High-performance ARM AMBA* AXI* bus bridges
      • AMBA AXI-3 compliant
      • Allows both independent and tightly coupled operation between HPS and logic core
      • Support simultaneous read and write transactions
    • FPGA-to-HPS bridge
      • Allows IP bus masters in the logic core to access to HPS bus slaves
      • Configurable 32, 64, or 128 bit AMBA AXI interface
      • Up to three masters within the core fabric can share the HPS SDRAM controller with the processor
    • HPS-to-FPGA bridge
      • Allows HPS bus masters to access to bus slaves in core fabric
      • Configurable 32, 64, or 128 bit Avalon® or AMBA AXI interface allows high-bandwidth HPS master transactions to logic core
    • Configuration bridge
      • Allows configuration manager in HPS to configure the logic core under program control via dedicated 32 bit configuration port
    • Light weight HPS-to-FPGA bridge
      • Light weight 32 bit AXI interface suitable for low-latency register accesses from HPS to soft peripherals in logic core
    • FPGA-to-HPS SDRAM controller bridge
      • Up to three masters (command ports), 3X 64 bit read data ports and 3X 64 bit write data ports