Intel® Arria® 10 SoC FPGAs integrate an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. It combines the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. The Arria 10 SoCs, based on TSMC’s 20 nm process technology, combine a dual-core ARM Cortex-A9 MPCore* HPS with industry-leading programmable logic technology that includes hardened floating-point digital signal processing (DSP) blocks.
Intel® Arria® 10 FPGAs deliver more than a speed grade faster core performance and up to a 20% Fmax advantage compared to the competition, using publicly-available OpenCores designs.1 In addition, the Arria 10 family offers the programmable logic industry’s only 20 nm ARM-based SoCs, delivering clock speeds at up to 1.5 GHz. The Arria 10 family also delivers the first hardened support for floating point operations in an FPGA, enabling a new level of DSP performance.
Learn more about Arria 10 core performance advantages and how you can prove them yourself >>
Arria 10 FPGA and SoC serial transceivers offer high bandwidth, low latency, and the lowest power to help you build high-speed communication systems2. Whether getting data across a board, distributing data to server blades across a backplane, moving data to the next chassis in a data center, or transporting data across the world through a sophisticated optical transport network, the Arria 10 FPGA and SoC transceivers provide a wide range of capabilities to support an extensive set of protocols and deliver reliable bandwidth at low cost.
Arria 10 FPGA and SoC Transceiver Applications
Arria 10 FPGA and SoC transceivers are well suited for:
Built on 20 nm process technology, the Arria 10 FPGAs and SoCs provide over 3.3 Tbps of total serial bandwidth. Arria 10 GX devices offer up to 96 channels at 17.4 Gbps for short-reach applications as well as up to 12.5 Gbps for backplane support. In addition, the Arria 10 GT FPGAs offers data rates up to 25.78 Gbps bringing high-end bandwidth performance into a midrange device.
Arria 10 FPGA and SoC Transceiver Features
The Arria 10 FPGA and SoC transceivers have a versatile feature set to handle a wide range of links and provide error-free link operation, including full-featured physical medium attachment (PMA) and hard physical coding sublayer (PCS) layers. In addition, dedicated PCI Express® (PCIe®) hard intellectual property (IP) blocks provide a full hardened protocol stack to support PCIe Gen1, Gen2, and Gen3x8. The following figure shows the rich set of capabilities that are available to implement high-speed serial links with benefits described.
| Features | Capability |
|---|---|
| Chip-to-chip data rates | 125 Mbps to 17.4 Gbps (Arria 10 GX devices) 125 Mbps to 25.78 Gbps (Arria 10 GT devices) |
| Backplane support | Drive backplanes at data rates up to 12.5 Gbps |
| Optical module support | SFP+/SFP, XFP, CXP, QSFP/QSFP28, CFP/CFP2/CFP4 |
| Cable driving support | SFP+ Direct Attach, PCIe over cable, eSATA |
| Transmit pre-emphasis | 5-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss. |
| Dual-Mode Continuous Time Linear Equalizer (CTLE) | High-gain and high-data rate mode receiver linear equalization to compensate system channel loss. |
| Decision Feedback Equalizer (DFE) | 11-fixed tap DFEs to equalize backplane channel loss in the presence of crosstalk and noisy environments. |
| Variable Gain Amplifier (VGA) | Broadband amplifier to maximize input dynamic range. |
| Altera Digital Adaptive Parametric Tuning(ADAPT) | All digital adaptation engine to automatically adjust all link equalization parameters—including CTLE, DFE, and VGA blocks—which provide optimal link margin without intervention from user logic. |
| Precision Signal Integrity Calibration Engine (PreSICE) | Hardened calibration controller to quickly calibrate all transceiver calibration parameters on power-up for optimal signal integrity performance. |
| ATX transmit Phased Locked-Loops (PLLs) | Ultra-low jitter LC (inductor-capacitor) transmit PLLs with continuous tuning range to cover a wide range of standard and proprietary protocols. |
| Clock Mulitpler PLLs (CMU PLL) | Ring oscillator-based transmit clock sources for multirate applications. |
| Fractional PLLs (fPLL) | On-chip fractional frequency synthesizers to replace on board crystal oscillators and reduce system cost. |
| Digitally-assisted hybrid Clock-Data Recovery (CDR) | Superior jitter tolerance with fast lock time with independent channel PLL. |
Download the Quartus® Prime software and implement transceiver designs today.
The three DSP block modes available are as follows:
In Arria 10 devices, Intel has enhanced the variable-precision DSP block by including hardened floating-point operators. The Arria 10 FPGA and SoC variable-precision DSP block introduces a new floating-point mode that delivers breakthrough floating-point performance of up to 1.5 TeraFLOPs.
The architectural innovation in the implementation of IEEE 754 single-precision hardened floating-point DSP (digital signal processing) blocks in Arria® 10 FPGAs and SoCs enable processing rates up to 1.5 TFLOPs (Tera Floating-point Operations Per Second) and power efficiency up to 40 GFLOPs/Watt.
With the three modes available for Arria® 10 DSP blocks: standard-precision fixed-point, high-precision fixed point and single-precision floating-point, designers can implement a variety of algorithms that require fixed point all the way to double-precision IEEE 754 compliant floating-point operations. Hardened floating-point processing offers designers the ability to implement algorithms in floating point with the similar performance and power efficiency as fixed point. This can be achieved without any power, area, or density compromises and with no loss of fixed-point features or functionality.
Arria 10 FPGAs and SoCs are a compelling solution for industrial, wireless systems, compute intensive applications such as high performance computing, machine learning, high-precision radars and data center acceleration applications.
A single DSP block in the floating-point mode provides an IEEE 754 single-precision floating-point multiplier and an IEEE 754 single-precision adder, delivering the highest floating-point performance on any FPGA in the market. These floating-point operators allow floating-point designs to be similar to traditional fixed-point designs, providing the benefits of floating-point at no additional cost for FPGA designers. Also, designers are able to remain in floating point, eliminating months of converting algorithms to fixed point and verifying the accuracy.
The floating-point mode offers:
In addition to floating-point capabilities, the new variable prevision block includes:
All DSP block modes feature a 64 bit accumulator and each variable-precision DSP block comes with a 64 bit cascade bus. The cascade bus allows the implementation of even higher precision signal processing through cascading multiple blocks using a dedicated bus.
The variable-precision DSP architecture maintains backward compatibility. It can efficiently support existing 18 bit DSP applications, such as high-definition video processing, digital up- or down- conversion and multirate filtering.
A complete suite of tools to accelerate designer’s productivity include model-based, C-based, and HDL/IP-based design entry
Need even more floating-point performance? Arria® 10 designs offer a seamless design and device migration path to Stratix 10 devices offering up to 10 TFLOPS of performance. For more information, contact your local sales representative.
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