AHCI 1.3.1 Technical Proposal
AHCI 1_3_1 TP001v8_11112011.doc
AHCI 1.3.1
AHCI 1.3.1
Device Sleep Technical Proposal
Device Sleep Technical Proposal
AHCI 1_3_1 TP001v8.doc
Please send comments to James Boyd
james.a.boyd@intel.com
AHCI Confidential
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AHCI 1_3_1 TP001v8_11112011.doc
AHCI 1.3.1 TR001v8
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Table of Contents
NEW PROGRAMMING REGISTER DEFINITIONS ....................................................................... 1
1.1 Description of Technical Changes .................................................................................................. 1
1.2 Description of Additions to Specification ........................................................................................ 1
3.1.5 Offset 10h: VS – AHCI Version ..................................................................................................................... 1
3.3 Port Registers (one set per port) ......................................................................................................... 2
3.3.7 Offset 18h: PxCMD – Port x Command and Status ...................................................................................... 4
3.3.17 Offset 44h: PxDEVSLP – Port x Device Sleep ............................................................................................ 6
3.3.10 Offset 28h: PxSSTS – Port x Serial ATA Status (SCR0: SStatus) .............................................................. 8
3.3.11 Offset 2Ch: PxSCTL – Port x Serial ATA Control (SCR2: SControl) ........................................................... 8
5.3 HBA Port State Machine (Normative) .................................................................................................. 9
5.3.1 Variables ..................................................................................................................................................... 10
5.3.2 Port Idle States ............................................................................................................................................ 11
5.3.2.1 P:Init ................................................................................................................................................... 11
5.3.4 Power Management States ............................................................................................................ 13
2 ADDITIONS TO SECTION 8 ............................................................................................ 17
2.1 Description of Technical Issue ...................................................................................................... 17
3 ADDITIONS TO SECTION 10 .......................................................................................... 20
3.1 Description of Technical Changes ................................................................................................ 20
3.2 Description of Changes to Specification ....................................................................................... 20
10.3.1 Start (PxCMD.ST) ..................................................................................................................................... 20
AHCI Confidential
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AHCI 1_3_1 TP001v8_11112011.doc
1 New Programming Register Definitions
1.1 Description of Technical Changes
To support the Device Sleep feature, AHCI requires the definition of new bits in existing registers and the
definition of an additional register. Device Sleep is a feature that allows the host and device to coordinate
turning off their respective PHYs (in order to conserve power). The additions to AHCI outline a method to
detect support (CAP2.SDS), for direct software control of this feature (via PxCMD.ICC), and a method for
HW to autonomously enter and exit DevSleep (PxDEVSLP.ADSE). Due to timing requirements of
entering and exiting DevSleep (to coordinate PHYs), programmable timing registers have also been
added to aid in optimizing resume latencies. PxDEVSLP.DITO is the time a given port must be idle
before HW may enter DevSleep autonomously. PxDEVSLP.DETO is the time reported by the device
before it can accept OOB signaling after the de-assertion of the DEVSLP signal from the host (software or
HW automated).
1.2 Description of Additions to Specification
Update sections as indicated in red
3.1.5 Offset 10h: VS – AHCI Version
This register indicates the major and minor version of the AHCI specification that the HBA implementation
supports. The upper two bytes represent the major version number, and the lower two bytes represent
the minor version number. Example: Version 3.12 would be represented as 00030102h. Three versions
of the specification are valid: 0.95, 1.0, 1.1, 1.2, 1.3, and 1.3.1.
3.1.5.1 VS Value for 0.95 Compliant HBAs
Bit Type Reset Description
31:16 RO 0000h Major Version Number (MJR): Indicates the major version is “0”
15:00 RO 0905h Minor Version Number (MNR): Indicates the minor version is “95”.
3.1.5.2 VS Value for 1.0 Compliant HBAs
Bit Type Reset Description
31:16 RO 0001h Major Version Number (MJR): Indicates the major version is “1”
15:00 RO 0000h Minor Version Number (MNR): Indicates the minor version is “0”.
3.1.5.3 VS Value for 1.1 Compliant HBAs
Bit Type Reset Description
31:16 RO 0001h Major Version Number (MJR): Indicates the major version is “1”
15:00 RO 0100h Minor Version Number (MNR): Indicates the minor version is “10”.
Read the full AHCI 1.3.1 Technical Proposal.