ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartus-11.1-2.dp8-readme.txt Readme file for Quartus II 11.1 SP2 Patch 2.dp8 Copyright (C) Altera Corporation 2012 All right reserved. Patch created on March 23 2012 Patch case#: 37447 //**************************************************************** Please note, this patch is meant to address known software issues for Stratix V and Arria V devices in the Quartus II software version 11.1 SP2. The device patches are cumulative. For example, you can install 2.dp8 over 2.dp3 or directly on top of 11.1 SP2. ====================================== The following were addressed in 2.dp3: ====================================== -------------------- Issue 1 (case 30142) -------------------- This patch fixes a problem with Partial Reconfiguration (PR), where M20K RAM blocks could not be used anywhere in the static region within the same columns of the chip as a PR region. This fix works around the issue by skipping programming of the RAM contents of partially- reconfigurable M20Ks. The consequence of this is that M20Ks can no longer have initialization values in the PR region. In other words, ROM mode and initialized RAMs are not supported for M20Ks in PR regions. A PR region containing such a block will silently fail. -------------------- Issue 2 (case 33240) -------------------- EDA Simulation Library Compiler GUI fails to detect QuestaSim executable -------------------- Issue 3 (case 33687) -------------------- Internal Error: Sub-system: ASMCC, File: /quartus/comp/asmcc/asmcc_bitfield.cpp, Line: 882 Assembler bitfield error: Found conflicting assignments for CRAM address; address = 4935431 This is due to ERAM content initialization occurs at the wrong side of ERAM array. It affects only M20K design with data width less than 16 bits and at the same time involves partial ERAM initialization with address width less than 11 bits. This affects only Stratix V devices. The fix allows the ERAM content initialization to be carried out correctly without rewriting into the same ERAM location. -------------------- Issue 4 (case 34215) -------------------- Internal Error: Sub-system: ASMIO, File: /quartus/comp/asmio/asmio_oct.cpp, Line: 714 !is_differential The Internal Error can happen for any Stratix V or Arria V design with pins that use parallel calibration and are using IO_STANDARD "DIFFERENTIAL 1.35-V SSTL". -------------------- Issue 5 (case 36304) -------------------- Quartus II triggers the following error when openning Chip Planner for Stratix V designs with DQS FF: Fatal Error: Access Violation at 0X000000001CED28C5 -------------------- Issue 6 (case 36305) -------------------- Alt_syncram timing paths for Stratix V M20K ECC modes have been made accurate. -------------------- Issue 7 (case 36307) -------------------- Address decoder in Stratix V soft XAUI had incorrect connection, making registers in address range 0x40 -0x7F inaccessible. -------------------- Issue 8 (case 36431) -------------------- When compiling with Quartus II software version 11.1sp2 and earlier, Arria V and Stratix V devices may malfunction in hardware. The malfunction is due to incorrect setting of unused bits in the transceiver memory initialization files (.mif). This problem occurs only for those designs that contain PLLs or transceiver reconfig controllers for Arria V and Stratix V devices. This patch provides a workaround for the problem. Workaround: 1) Use 11.1sp2 2.dp3 or later version of the Quartus II software to compile your design 2) Add the following INI variable(s) in the quartus.ini file in the project directory: fsv_hssi_reconfig_qic_enhancement=on For compilations that use Quartus II Incremental Compilation (QIC) flow and are preserving all partitions containing transceiver reconfig IP, transceivers, pll and periphery logic, add the following INI variable too: fsv_hssi_reconfig_skip_writing_mapping_in_qic_flow=on * WARNING: You should NOT use the second INI variable if you're not using Quartus II Incremental Compilation (QIC) flow or are not preserving all partitions containing transceiver reconfig IP, transceivers, pll and periphery logic, otherwise, hardware failure may be encountered. * All partitions containing transceiver reconfig IP, transceivers, PLls and periphery logic must be using the same netlist type setting (Post-Synthesis or Post-Fit). No other configurations are supported until 12.0. This issue will be fixed in a future version of the Quartus II software, after which these INI variables will not be needed. ===================================================================== The following were addressed in 2.dp6:(2.dp6 includes fixes in 2.dp3) ===================================================================== -------------------- Issue 9 (case 38000,38001,38002,38004,38069, 38317, 40065) -------------------- For Stratix V A7/A5/B6 ES parts, the clock network and some routing delays to and from registers in the IO's have been updated based on Silicon and simulation data. For Stratix V B6 ES parts, the settings for PLLs used for LVDS have been updated to increase the margin for LVDS transfers. For Arria V parts, routing, clock and DSP block delays have been updated based on additional simulation results and from initial Silicon data. --------------------- Issue 10 (case 38138) --------------------- There is a silicon bug in Stratix V ES devices that is due to DQS logic blocks, that connect to the IOs, have crosswired connections. The IOs affected by this silicon bug will not behave as expected by the user. The patch provides a software workaround which ensures that if a design uses an affected IO, it will behave according to what the user expects. --------------------- Issue 11 (case 39328) --------------------- This patch enables LVDS package skew compensation report for Stratix V devices. --------------------- Issue 12 (case 38458) --------------------- Internal Error: Sub-system: ASMIO, File: /quartus/comp/asmio/asmio_buf.cpp, Line: 2289 pullup_strength > 0 && pullup_strength < 255 This Internal Error can happen for any Stratix V design with an output pin that the sole configuration of it is to drive out a GND signal, in other words, if the pin is not connected to any logic. --------------------- Issue 13 (case 38038) --------------------- Internal Error: Sub-system: ASMDB, File: /quartus/db/asmdb/asmdb_mux.cpp, Line: 363 ASMDB_MUX error: get_bit_value : index out of range (index = 37, size = 18) This Internal Error will occur when using PCIe with Hard IP (HIP) for Stratix V f4 production devices. It will not occur for Stratix V f5, ES devices or if you're not using PCIe with HIP. ===================================================================== The following were addressed in 2.dp7:(2.dp7 includes fixes in 2.dp3 and 2.dp6) ===================================================================== --------------------- Issue 14 (case 40477) --------------------- Reconfiguration IP may start operating before the transceiver PHY is ready. Invalid values might be written into the transceiver causing incorrect CMU PLL operation. This issue affects Arria V designs with transceivers. After installing Patch 2.dp7 or later version of the Quartus II software, regenerate Reconfiguration IP to fix this issue and do a fresh compilation. --------------------- Issue 15 (case 40492) --------------------- TX PLL/CDR of some ES devices may not lock to refclk upon power-up or after reset. This issue affects Arria V designs with transceivers. After installing Patch 2.dp7 or later version of the Quartus II software, regenerate PHY and Reconfiguration IP to fix the PMA reset sequencing and do a fresh compilation. ===================================================================== The following were addressed in 2.dp8:(2.dp8 includes fixes in 2.dp3,2.dp6,2.dp7) ===================================================================== --------------------- Issue 16 (case 43313) --------------------- This patch updates Stratix V timing for routing wires in the A5/A7 ES parts. --------------------- Issue 17 (case 41577) --------------------- This patch adds device support for Arria V 5AGXFB3H4F35I5ES device. Caution - You must either have previously installed the Quartus II 11.1 SP2 software or must install the Quartus II 11.1 SP2 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.