ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH
WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH
WILL BE UNINTERRUPTED OR ERROR-FREE.

//****************************************************************
quartus-11.1-2.dp3-readme.txt
Readme file for Quartus II 11.1 SP2 Patch 2.dp3
Copyright (C) Altera Corporation 2012 All right reserved.
Patch created on February 13 2012
Patch case#: 37447
//****************************************************************

Please note, this patch is meant to address known software issues for
Stratix V and Arria V devices in the Quartus II software version 11.1 SP2.


======================================
The following were addressed in 2.dp3:
======================================
--------------------
Issue 1 (case 30142)
--------------------
This patch fixes a problem with Partial Reconfiguration (PR), where
M20K RAM blocks could not be used anywhere in the static region within
the same columns of the chip as a PR region. This fix works around the
issue by skipping programming of the RAM contents of partially-
reconfigurable M20Ks. The consequence of this is that M20Ks can no
longer have initialization values in the PR region.  In other words,
ROM mode and initialized RAMs are not supported for M20Ks in PR
regions. A PR region containing such a block will silently fail.

--------------------
Issue 2 (case 33240)
--------------------
EDA Simulation Library Compiler GUI fails to detect QuestaSim
executable

--------------------
Issue 3 (case 33687)
--------------------
Internal Error: Sub-system: ASMCC, 
File: /quartus/comp/asmcc/asmcc_bitfield.cpp, Line: 882
Assembler bitfield error: Found conflicting assignments for CRAM address; address = 4935431

This is due to ERAM content initialization occurs at the wrong side of
ERAM array. It affects only M20K design with data width less than 16
bits and at the same time involves partial ERAM initialization with
address width less than 11 bits. This affects only Stratix V
devices. The fix allows the ERAM content initialization to be carried
out correctly without rewriting into the same ERAM location.

--------------------
Issue 4 (case 34215)
--------------------
Internal Error: Sub-system: ASMIO, 
File: /quartus/comp/asmio/asmio_oct.cpp, Line: 714
!is_differential

The Internal Error can happen for any Stratix V or Arria V design with
pins that use parallel calibration and are using IO_STANDARD
"DIFFERENTIAL 1.35-V SSTL".

--------------------
Issue 5 (case 36304)
--------------------
Quartus II triggers the following error when openning Chip Planner for
Stratix V designs with DQS FF:
Fatal Error: Access Violation at 0X000000001CED28C5

--------------------
Issue 6 (case 36305)
--------------------
Alt_syncram timing paths for Stratix V M20K ECC modes have been made accurate.

--------------------
Issue 7 (case 36307)
--------------------
Address decoder in Stratix V soft XAUI had incorrect connection,
making registers in address range 0x40 -0x7F inaccessible.

--------------------
Issue 8 (case 36431)
--------------------
When compiling with Quartus II software version 11.1sp2 and earlier,
Arria V and Stratix V devices may malfunction in hardware.  The
malfunction is due to incorrect setting of unused bits in the
transceiver memory initialization files (.mif).

This problem occurs only for those designs that contain PLLs or
transceiver reconfig controllers for Arria V and Stratix V devices.

This patch provides a workaround for the problem. 

Workaround:

1) Use 11.1sp2 2.dp3 or later version of the Quartus II software to
   compile your design

2) Add the following INI variable(s) in the quartus.ini file in the
   project directory:

     fsv_hssi_reconfig_qic_enhancement=on

   For compilations that use Quartus II Incremental Compilation (QIC)
   flow and are preserving all partitions containing transceiver
   reconfig IP, transceivers, pll and periphery logic, add the
   following INI variable too:

     fsv_hssi_reconfig_skip_writing_mapping_in_qic_flow=on

    * WARNING: You should NOT use the second INI variable if you're
      not using Quartus II Incremental Compilation (QIC) flow or are
      not preserving all partitions containing transceiver reconfig
      IP, transceivers, pll and periphery logic, otherwise, hardware
      failure may be encountered.

    * All partitions containing transceiver reconfig IP, transceivers,
      PLls and periphery logic must be using the same netlist type
      setting (Post-Synthesis or Post-Fit).  No other configurations
      are supported until 12.0.

This issue will be fixed in a future version of the Quartus II
software, after which these INI variables will not be needed.


Caution - You must either have previously installed the
          Quartus II 11.1 SP2 software or must
          install the Quartus II 11.1 SP2 software
          before installing this patch. Otherwise, the patch will
          not be installed correctly and the Quartus II
          software will not run properly.