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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate

Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate

This paper describes integration of an advanced composite High-K gate stack (4nm TaSiOx-2nm InP) in the In0.7Ga0.3As quantum-well field effect transistor (QWFET) on silicon substrate. The composite High-K gate stack enables both (i) thin electrical oxide thickness (tOXE) and low gate leakage (JG) and (ii) effective carrier confinement and high effective carrier velocity (Veff) in the QW channel. The LG=75nm In0.7Ga0.3As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at VDS=0.5V.

In0.7Ga0.3As QWFET is a promising transistor candidate for future high-speed low-power logic applications due to its excellent drive current performance at low voltage, and its demonstrated integration onto the silicon substrate [1]. However at present the InGaAs QWFET uses a Schottky gate with no gate dielectric and is subjected to large gate leakage (JG) with scaling of the upper InAlAs barrier thickness above the quantum well (QW) (Fig. 1). For further transistor scaling, there are significant challenges in identifying a suitable high dielectric constant (K) gate dielectric and its integration into the III-V transistor, which will need to simultaneously decrease tOXE (electrical gate oxide thickness), reduce JG, achieve good interface properties while retaining high carrier mobility in the transistor channel. In this work, we demonstrate a composite high-K TaSiOx-InP gate stack and its integration into the In0.7Ga0.3As QWFET, resulting in high-performance short-channel In0.7Ga0.3As QWFETs on silicon substrate with significantly decreased tOXE and reduced JG.

Read the full Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate Paper.

Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate

This paper describes integration of an advanced composite High-K gate stack (4nm TaSiOx-2nm InP) in the In0.7Ga0.3As quantum-well field effect transistor (QWFET) on silicon substrate. The composite High-K gate stack enables both (i) thin electrical oxide thickness (tOXE) and low gate leakage (JG) and (ii) effective carrier confinement and high effective carrier velocity (Veff) in the QW channel. The LG=75nm In0.7Ga0.3As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at VDS=0.5V.

In0.7Ga0.3As QWFET is a promising transistor candidate for future high-speed low-power logic applications due to its excellent drive current performance at low voltage, and its demonstrated integration onto the silicon substrate [1]. However at present the InGaAs QWFET uses a Schottky gate with no gate dielectric and is subjected to large gate leakage (JG) with scaling of the upper InAlAs barrier thickness above the quantum well (QW) (Fig. 1). For further transistor scaling, there are significant challenges in identifying a suitable high dielectric constant (K) gate dielectric and its integration into the III-V transistor, which will need to simultaneously decrease tOXE (electrical gate oxide thickness), reduce JG, achieve good interface properties while retaining high carrier mobility in the transistor channel. In this work, we demonstrate a composite high-K TaSiOx-InP gate stack and its integration into the In0.7Ga0.3As QWFET, resulting in high-performance short-channel In0.7Ga0.3As QWFETs on silicon substrate with significantly decreased tOXE and reduced JG.

Read the full Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate Paper.

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