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Chip Chat: Jim Greene on Data Center Security

Chip Chat’s Allyson Klein interviews Jim Greene, discussing the future of data center security, how to stay ahead of threats, and his new book.

Jasper Forest From Intel Animation

Video introduces Jasper Forest: the newest addition to the Intel® Xeon® processor family.

Intel® Architecture: Powering a World of Storage

Video: Intel® Architecture, powerful, efficient, scalable, flexible storage solutions.

Strained Germanium QWFE Transistor as P-Channel Device Option for Low Power III-V CMOS Architecture

Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.

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High-κ Gate Dielectrics, Metal Gate Electrodes in Silicon and Non-Silicon Logic Nanotechnology

Discusses low gate-leakage silicon and non-silicon transistor nanotechnology using high-κ gate dielectrics and metal gate electrodes.

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High-k/Metal-Gate Stack and Its MOSFET Characteristics

Article, IEEE Election Device Letters, Vol 25, No. 6, June 2004: High-k/Metal-Gate Stack and Its MOSFET Characteristics.

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Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K

Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.

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Video Animation: Mark Bohr Gets Small: 22nm Explained

Mark Bohr explains how Intel 3-D transistors manufactured at 22nm ensure the pace of technology advancement for years to come.

Evaluation/Transport Physics: Schottky-Gate III-V Compound Semiconductor QWFE Transistors

Paper examines and evaluates logic performance of Schottky-gate QWFETs against that of advanced Strained Si MOSFETs in low power voltages.

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