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Introduction to Intel’s 32nm Process Technology

White Paper: Intel has been in high volume manufacturing on 32nm process technology with 2nd generation high-k + metal gate transistors since 2009.

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Intel presents Cedar Trail next-gen Atom platform at IDF 2011

Video: Intel presents Cedar Trail next-gen Atom™ platform at IDF 2011.

Advanced High-K Gate Dielectric for Short-Channel in QWFE Transistors on Silicon Substrate

Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.

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Strained Germanium QWFE Transistor as P-Channel Device Option for Low Power III-V CMOS Architecture

Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.

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High-κ Gate Dielectrics, Metal Gate Electrodes in Silicon and Non-Silicon Logic Nanotechnology

Discusses low gate-leakage silicon and non-silicon transistor nanotechnology using high-κ gate dielectrics and metal gate electrodes.

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Intel® Active Management Technology for Embedded Applications

Webinar describes Intel® Active Management Technology, a key part of Intel® vPro™ technology that enables remote management of embedded clients.

Intel® Active Management Technology (Intel® AMT) in Retail

Intel® Active Management Technology helps your retail connected in-store devices stay current, available and protected with energy efficiency.

Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K

Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.

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High-k/Metal-Gate Stack and Its MOSFET Characteristics

Article, IEEE Election Device Letters, Vol 25, No. 6, June 2004: High-k/Metal-Gate Stack and Its MOSFET Characteristics.

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Intel Global Manufacturing Facts

Fact Sheet: Intel Global Manufacturing

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