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Serial ATA AHCI 1.0 Specification

Serial TATAA Serial A Advanced Host Controller cInterfacee Advanced Host Controller Interfa I(AHCI)) (AHC Revision 1.0 Please send comments to Amber Huffman amber.huffman@intel.com i Table of Contents INTRODUCTION ............................................................................................................. 1 1 1.1 Overview.........................................................................................................................................1 1.2 Scope..............................................................................................................................................1 1.3 Outside of Scope ............................................................................................................................1 1.4 Block Diagram ................................................................................................................................1 1.5 Conventions....................................................................................................................................3 1.6 Terminology....................................................................................................................................4 1.7 Theory of Operation........................................................................................................................4 1.8 Interaction with Legacy Software....................................................................................................5 1.9 References .....................................................................................................................................5 2 HBA CONFIGURATION REGISTERS................................................................................... 6 2.1 PCI Header.....................................................................................................................................6 2.1.1 Offset 00h: ID - Identifiers ......................................................................................................................6 2.1.2 Offset 04h: CMD - Command.................................................................................................................6 2.1.3 Offset 06h: STS - Device Status.............................................................................................................7 2.1.4 Offset 08h: RID - Revision ID .................................................................................................................7 2.1.5 Offset 09h: CC - Class Code..................................................................................................................7 2.1.6 Offset 0Ch: CLS – Cache Line Size .......................................................................................................7 2.1.7 Offset 0Dh: MLT – Master Latency Timer ..............................................................................................8 2.1.8 Offset 0Eh: HTYPE – Header Type........................................................................................................8 2.1.9 Offset 0Fh: BIST – Built In Self Test (Optional)......................................................................................8 2.1.10 Offset 10h – 20h: BARS – Other Base Addresses (Optional) ................................................................8 2.1.11 Offset 24h: ABAR – AHCI Base Address ...............................................................................................8 2.1.12 Offset 2Ch: SS - Sub System Identifiers ................................................................................................8 2.1.13 Offset 30h: EROM – Expansion ROM (Optional) ...................................................................................8 2.1.14 Offset 34h: CAP – Capabilities Pointer...................................................................................................9 2.1.15 Offset 3Ch: INTR - Interrupt Information ................................................................................................9 2.1.16 Offset 3Eh: MGNT – Minimum Grant (Optional).....................................................................................9 2.1.17 Offset 3Fh: MLAT – Maximum Latency (Optional) .................................................................................9 2.2 PCI Power Management Capabilities.............................................................................................9 2.2.1 Offset PMCAP: PID - PCI Power Management Capability ID.................................................................9 2.2.2 Offset PMCAP + 2h: PC – PCI Power Management Capabilities...........................................................9 2.2.3 Offset PMCAP + 4h: PMCS – PCI Power Management Control And Status........................................10 2.3 Message Signaled Interrupt Capability (Optional)........................................................................10 2.3.1 Offset MSICAP: MID – Message Signaled Interrupt Identifiers ............................................................10 2.3.2 Offset MSICAP + 2h: MC – Message Signaled Interrupt Message Control..........................................10 2.3.3 Offset MSICAP + 4h: MA – Message Signaled Interrupt Message Address ........................................11 2.3.4 Offset MSICAP + (8h or Ch): MD – Message Signaled Interrupt Message Data..................................11 2.3.5 Offset MSICAP + 8h: MUA – Message Signaled Interrupt Upper Address (Optional)..........................11 2.4 Other Capability Pointers..............................................................................................................11 3 HBA MEMORY REGISTERS ........................................................................................... 12 3.1 Generic Host Control ....................................................................................................................12 3.1.1 Offset 00h: CAP – HBA Capabilities.....................................................................................................12 3.1.2 Offset 04h: GHC – Global HBA Control................................................................................................13 3.1.3 Offset 08h: IS – Interrupt Status Register.............................................................................................14 3.1.4 Offset 0Ch: PI – Ports Implemented.....................................................................................................14 3.1.5 Offset 10h: VS – AHCI Version ............................................................................................................14 3.2 Vendor Specific Registers ............................................................................................................15 3.3 Port Registers (one set per port) ..................................................................................................15 3.3.1 Offset 100h: P0CLB – Port 0 Command List Base Address.................................................................15 3.3.2 Offset 104h: P0CLBU – Port 0 Command List Base Address Upper 32-bits........................................15 3.3.3 Offset 108h: P0FB – Port 0 FIS Base Address ....................................................................................15 3.3.4 Offset 10Ch: P0FBU – Port 0 FIS Base Address Upper 32-bits...........................................................16 3.3.5 Offset 110h: P0IS – Port 0 Interrupt Status ..........................................................................................16 ii 3.3.6 Offset 114h: P0IE – Port 0 Interrupt Enable .........................................................................................17 3.3.7 Offset 118h: P0CMD – Port 0 Command .............................................................................................18 3.3.8 Offset 120h: P0TFD – Port 0 Task File Data........................................................................................20 3.3.9 Offset 124h: P0SIG – Port 0 Signature ................................................................................................20 3.3.10 Offset 128h: P0SSTS – Port 0 Serial ATA Status (SCR0: SStatus).....................................................20 3.3.11 Offset 12Ch: P0SCTL – Port 0 Serial ATA Read the full Serial ATA AHCI 1.0 Specification.

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