During the functional and architectural design steps, developers create a virtual architecture model of the system, simply called "virtual system." This represents an abstraction of the final system and provides developers with means to validate the entire system through simulation. At this stage, it is essential to define the right abstraction level since it impacts simulation time and effectiveness. For instance, a low-level simulation such as RTL simulation is precise but slow. Evaluating complex systems requires faster simulation speed so they can be used in an interactive development process. However, a description at a higher abstraction level has to be precise enough to represent accurate real-time system behavior and to generate code for lower-level-virtual prototype simulation or implementation and synthesis purposes.
A model describes three types of views on a system:
There are typically five levels of abstraction for all models: service, message, transaction, transfer, and register transfer (or logic/gate).1
The communications view is the most significant view for characterizing an abstraction level. Each abstraction level has a corresponding model for communications defined by time accuracy, dependency as well as types of media, addressing, data and protocol.
|Abstraction levels||Characteristics of communications model|
|Service (e.g. CORBA)||Un-timed functional||Abstract Network||Automatic||Service request: do something||Abstract||Unpredictable (service/request causality)|
|Message (e.g. MCSE, SDL, UML)||(Un-) Timed functional||Logical network of active channels||Abstract & explicit||High-level primitives: send/recieve||Abstract||Possibly predictable (ordering of messages)|
|Transaction (e.g. CSP, SystemC Cossap)||Bus cycle-accurate||Logical links||Logical & explicit||Read/write data, wait for new event||Varying size||Synchronized to bus cycle|
|Transfer (e.g. VHDL, Verilog)||Cycle-accurate||Logical links||Logical & explicit||Read/write data, wait for new clock cycle||Fixed size||Synchronized to clock cycle|
|Register transfer (e.g. VHDL, Verilog)
||Pin-accurate||Physical links||Physical & explicit||Set/reset ports, wait for new clock cycle||Bit/data on bus||Synchronized to clock cycle|
Simulation speed and behavioral real-time accuracy depends on the abstraction levels at which communications and computation, as part of the behavioral view, are described. They also largely impact the complexity of the simulation environment and the exploitability of results obtained. Service and message level models are simulated on the development host platform using a native technology such as SystemC (host-based simulation), while lower level models require dedicated target hardware. RTL and transaction level simulation technologies are closer to a real world execution than higher level models, but significant results can be difficult to obtain.
Intel® CoFluent™ Studio creates different models at the message level. Models are precise and fully timed to simulate real time behavior. The high level abstraction enables high-speed simulation (about 1000x RTL simulation speed). In addition, they provide high level simulation results for early and easy evaluation, avoiding any paradigm shift from modeling to analysis.
Flexible architecture modeling capabilities enable designers to explore multiple architectural choices. Performances analysis is based on simple configuration parameters describing macroscopic properties of architectural components. It does not require separate simulation or special system editing.
Developers can no longer use low-level represenatations (RTL for hardware, assembly for software) to develop systems. Higher abstraction levels are required to master complexity and reduce development times.
Software needs to be validated before the final hardware is available.
1. Abstraction levels definition and table courtesy of Jean Paul Calvez and Gabriela Nicolescu, excerpt from chapter 2 Spécification et modélisation des systèmes embarqués of the book edited by A. A. Jerraya and G. Nicolescu: La spécification et la validation des systèmes hétérogènes embarqués (publisher: Hermes, Collection "Techniques de l'ingénieur").